Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD typically includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, programming data is stored on-chip in non-volatile memory. In some CPLDs, programming data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial programming sequence.
FIG. 1 is a simplified illustration of an exemplary CPLD. A CPLD typically includes two or more logic blocks (LBs 101a-101h) connected together and to input/output blocks (I/Os 102a-102f) by a programmable interconnection array (103). The interconnection array includes many multiplexer circuits 105, each including several programmable interconnect points (PIPs) 104. In each multiplexer circuit 105, only one PIP 104 is enabled. The enabled PIP selects one of the many input signals provided to the interconnection array, and the selected input signal is provided as the output signal from the multiplexer circuit 105.
Many PLDs that store data in non-volatile memory, including many CPLDs, provide the capability of erasing programming data previously stored in the device, and replacing the programming data with a new data stream. For example, the use of FLASH memory to store the programming data renders a PLD reprogrammable. This capability can be extremely useful, for example, in testing the PLD prior to sale. Many different configurations can be programmed into the device, and functionality can be verified in many different ways. The programming data used for testing can then be erased, and the PLD can be sold as a reprogrammable PLD.
However, there are applications in which reprogrammability is a drawback. For example, in a slot machine, the ability to reprogram a PLD might render the slot machine vulnerable to tampering, e.g., with the objective of changing the pay out rate. For this type of application, “one time programmable” (OTP) devices are sometimes preferred. An OTP device can be programmed only once. Once the device is programmed with a first set of programming data, the device cannot be reprogrammed and the programming data cannot be erased. One way of implementing an OTP device is to use fuse structures. Once a fuse is blown, the nodes on either side of the fuse cannot be reconnected. Therefore, the programming is permanent. Mask programmable gate arrays provide another type of OTP device. Mask programmable gate arrays are also relatively inflexible, being permanently “programmed” during fabrication.
Clearly, a manufacturer cannot test an OTP device by repeatedly programming the devices with different configurations, as is normal procedure with reprogrammable PLDs. Therefore, an OTP device can only be fully tested after programming, e.g., by a user implementing a user design in the OTP device. A certain percentage of these devices will fail the tests, possibly necessitating further tests to determine the source of the problem so the user can be reimbursed for faulty devices. Therefore, it is desirable to provide circuits and methods that enable the testing of OTP devices more fully prior to programming the devices with the permanent configuration.
Another drawback of known OTP devices is that a design cannot be “debugged” by making alterations to the design as errors become apparent, and loading the altered design back into the device, because the design programmed into the OTP device is permanently fixed. Therefore, it is desirable to provide circuits and methods for OTP devices that enable the alteration of a design programmed into the device during a debug phase for the design.